Fully Differential Receiver Chipset for 40 Gb/s Applications Using GaInAs/InP Single Heterojunction Bipolar Transistors

Advent of multimedia applications, which require data links with ever-increasing capacity, is necessitating highspeed optical communication systems and driving research and development for high-speed ICs operating at 40 Gb/s. These optical fiber communication systems require high performance and low power chipsets, which incorporate useful service functions. Figure 1 illustrates a typical receiver block diagram. The transimpedance amplifier (TIA) converts the current variations generated by the photodetector to an amplified voltage swing at its output. A limiting amplifier, by providing a large dynamic range and a constant limited output, is generally utilized to further shape the signal received from the TIA. The serial high-bit rate data are then passed through a clock and data recovery stage (CDR) for further signal shaping and demultiplexed down to multiple parallel lanes at lower bit rates for easy interfacing with the transport / service ICs, such as de-framers, and finally passed on to network processors for further manipulation.